1. Field of the Invention
The present invention relates to a programmable delay circuit. More precisely, the present invention relates to a programmable delay circuit that regulates delay time with a variable resistance unit and a variable capacitance unit.
2. Description of Related Art
Programmable delay circuits are indispensable components of many integrated circuits. For example, delay-locked loops, data transmission interfaces, and various circuits for phase comparison must use the programmable delay circuits. Therefore, it is the goal of many research institutes to design a programmable delay circuit with powerful functions.
FIG. 1 is a schematic structural view of a conventional programmable delay circuit. Referring to FIG. 1, the conventional programmable delay circuit 100 is mainly formed by coupling inverters 101 and 102, and the delay time between an input signal VIN1 and an output signal VOUT1 is determined by the driving capability of the inverter 101. The conventional programmable delay circuit 100 uses a delay-controlled code b[K:1] to control an ON/OFF states of PMOS transistors MP11-MP1K and NMOS transistors MN11-MN1K, so as to regulate a current I1 flowing through the inverter 101, where K is a positive integer. Thus, along with the change of current I1, the delay time between the input signal VIN1 and the output signal VOUT1 changes accordingly.
However, with reference to a simulation diagram of the conventional delay circuit 100 of FIG. 2, it can be known according to a characteristic curve of the delay-controlled code to the delay time that the linearity of the delay time controlled by the conventional delay circuit 100 is very poor, and the range of regulation is quite narrow. In addition, the conventional delay circuit 100 requires a relatively large layout area to accommodate the PMOS transistors MP11-MP1K and the NMOS transistors MN11-MN1K.
FIG. 3 is a schematic structural view of another conventional programmable delay circuit. Referring to FIG. 3, a conventional programmable delay circuit 300 is also mainly formed by coupling inverters 302 and 302, and the delay time between an input signal VIN3 and an output signal VOUT3 is also determined by the driving capability of the inverter 301. Here, PMOS transistors MP31-MP3L and NMOS transistors MN31-MN35 constitute a digital control current mirror, in which L is a positive integer. The digital-controlled current mirror regulates a current I3 flowing through the inverter 301 according to a delay-controlled code b[L:1], so as to achieve the purpose of regulating the delay time.
When a delay-controlled code b[L:1] is at a high level, in order to make the programmable delay circuit 300 operate normally, the digital-controlled current mirror must include a small-sized PMOS transistor MP35, so as to provide a micro current I3 to the inverter 301. However, the micro current I3 will influence the maximum delay time and the minimum delay time that can be provided by the conventional programmable delay circuit 300. In addition, with reference to a simulation diagram of the conventional programmable delay circuit 300 of FIG. 4, it can be known that the i range of corner overlap of the delay time controlled by the conventional programmable delay circuit 300 is wider, but the curve is still non-linear.
FIG. 5 is a schematic structural view of still another conventional programmable delay circuit. Referring to FIG. 5, a conventional programmable delay circuit 500 is mainly formed by coupling inverters 501 and 502, and the delay time between an input signal VIN5 and an output signal VOUT5 is determined by the equivalent capacitance on the output end of the inverter 501. Here, the conventional programmable delay circuit 500 uses a delay-controlled code b[S:1] to control the ON/OFF states of NMOS transistors MN51-MN5S, so as to regulate the influence of load capacitors C51-C5S on the output end of the inverter 501.
However, in order to prevent the delay effect formed by the parasitic resistance of the NMOS transistors NM51-NM5S and the load capacitors C51-C5S, the width of the NMOS transistors NM51-NM5S and the size of the load capacitors C51-C5S for the conventional programmable delay circuit 500 must be increased to achieve the optimal design. In addition, with reference to a simulation diagram of the conventional programmable delay circuit 500 of FIG. 6, it is known that the range of corner overlap of the delay time controlled by conventional programmable delay circuit 500 is very narrow.